The present invention relates to a semiconductor device, and more particularly, to a method for forming patterns by using a mixed assist feature system to transfer an accurate image on a boundary region between pattern dense region and pattern isolated region of substrate.
A microlithography process is carried out for realizing the semiconductor device on a wafer as circuit patterns. The microlithography process includes designing a layout of the patterns to be realized on a wafer and forming a photomask in which the designed pattern layout is realized on a transparent mask substrate as mask patterns. Then, the mask patterns are transferred onto a photoresist layer coated on the wafer through an exposure process using the photomask, thereby forming a photomask that follows the designed pattern layout. After that, a selective etch process using the photoresist patterns as an etch mask is carried out, thereby realizing, on the wafer, wafer patterns or target patterns that follows the designed pattern layout.
As a design rule of memory semiconductor devices such as a DRAM device and a NAND flash device is decreased, it is required a process of realizing patterns of finer critical dimension on the wafer. The process margin for exposing these fine patterns may vary in regions on the wafer depending on the density of the patterns to be transferred. For example, the process margin window such as a defocus margin may be relatively narrowed in a region having relatively large spacing distance between the patterns, resulting in pattern transfer failures such as distortion of a pattern shape.
At a vicinity of a dense pattern region on the wafer such as a cell region in which cell patterns for unit memory cells are disposed, an isolated pattern region may be disposed. The isolated pattern region may include a peripheral in which a word line driver is disposed and a core region in which a sub word line driver is disposed. At this time, the patterns disposed in a boundary region between the regions may be transferred onto the wafer with their shape or form being undesirably deformed.
The cell patterns in the cell region are disposed so as to have substantially equal shape and spacing distance. However, in case of the cell patterns located at cell region and a region outside the cell region, e.g. a boundary between core regions, a first spacing distance from another pattern disposed outside the cell region is set to be relatively larger than a second spacing distance from adjacent another pattern disposed inside the cell region. Therefore, exposure environment or interference degree between exposing lights in the boundary region applied when the cell patterns located in the boundary region is transferred onto the wafer through the exposure differs from the exposure environment or interference degree between exposing lights inside the cell region applied to the cell patterns disposed inside the cell region.
When carrying out the exposure employing same exposure environment or variables, the pattern transfer for cell patterns inside the cell region can be relatively accurately carried out, but the pattern transfer for cell patterns disposed in the boundary region may result in pattern defect in which the pattern shape is distorted. Therefore, the process margin of the exposure condition in which the cell patterns in the boundary region are transferred with an accuracy of a desired level becomes very narrow. For example, during the course of transferring an isolation pattern for realizing an active region with a target critical dimension of about 50 nm, it could be appreciated that extremely poor pattern transfer onto the boundary region is resulted under the defocus condition of about 0.29 μm when condition for the best exposure focus is 0.21 μm. That is to say, even minute defocus of several tens of namometers results in the poor pattern transfer.
Since memory semiconductor devices require a process of transferring and realizing patterns having various shapes, sizes and spacing distances onto the wafer, it is very difficult to realize a pattern forming process that is stable over the entire wafer with this very narrow defocus margin. Further, in order to overcome resolution limitation in the exposure process and realize the patterns of fine critical dimension on the wafer, an asymmetric illumination such as a dipole illumination has been introduced. This dipole illumination can improve image contrast to the pattern extending in a direction perpendicular to a pole axis along which corresponding two poles are disposed and thus enhance the resolution. However, this dipole illumination is accompanied with lowering in the resolution for the pattern extending in a direction parallel to the pole axis.
As the asymmetric illumination that provides asymmetric resolution to extension directions of the patterns is introduced as described above, factors causing the pattern defect act more seriously on the pattern disposed in the boundary region. Accordingly, the poor pattern transfer onto the patterns disposed in the boundary is more serious as the more extreme asymmetric illumination is introduced. That is to say, since the defocus margin becomes very narrow, it becomes more difficult to ensure the process margin in the exposure process for pattern transfer.
When the poor pattern transfer is caused in the boundary region, various defects may be caused in the patterns of another layer which is formed in alignment with this transferred pattern in the follow-up processes. For example, when a pattern for defining an isolation structure or an active region is transferred poorly in the boundary region, a pattern defect such as a bridge may be caused in gates of transistor that is formed so as to cross the subsequently formed active region.
Therefore, it is required a method for transferring patterns disposed in the boundary region between the cell region, in which patterns are densely disposed, and an outer core region or a peripheral region onto the wafer with more accuracy and no shape distortion.